Memory is cyclical. But demand is inflecting faster than supply.

The reflexive view

What skeptics believe

“Memory is cyclical, everyone knows that, and the recent run in memory names is an obvious bubble.”

That call has paid off before, and it likely will again. Memory has cost growth investors more money than almost any product in tech. Memory typically goes through cycles:

1. A demand shock hits the industry and pushes memory prices up.
2. Memory makers race to add capacity to meet it.
3. The capacity overshoots, and the market tips into a supply glut.
4. The glut crashes prices — forcing losses, consolidation, and a pullback in investment that seeds the next upswing.

“Short memory into euphoria” has been a reliable rule for decades. But a rule is not an argument. Every past cycle ran on the same demand base (PCs, phones, servers, etc.) that you could count in devices, and supply has generally caught up. Calling memory “cyclical” assumes that base hasn’t changed. AI is the reason to check.

Every company is cyclical on a long enough timescale; what differs is the length of the cycle. What’s new here is the scale and durability of AI demand, hitting an industry that can’t add the right supply quickly.

The reframe

The three engines of memory demand

When it comes down to DRAM bits. HBM is built on them, and the bits equation is the simplest place to start — even if, as the bar for frontier AI rises, those bits are arguably no longer fungible.

When LLMs reached the public with GPT-3.5 in 2022, they were chatbots: one question, one answer. They’ve since become agentic systems that take actions and finish tasks, a shift that only got going in late 2025. That’s what’s inflecting memory demand, and it does so through three dynamics that each affect demand differently.

These engines are not strictly additive. More usage means more revenue, which powers scaling efforts. Scaling brings more intelligence, which unlocks new long-running capabilities like deep research and agentic coding. Long running tasks require larger context, etc. Three rising curves, several of them compounding, add up to a memory bill that climbs steeply rather than gradually. Next is how that reaches HBM.

The track record

Most of this already happened

Before trusting any 2030 number, look at where these engines already are — in production, on the public record. The demand drivers have run 50× to 1,000× in a handful of years. HBM supply, the hardware underneath them, has managed about a doubling in the last year. That gap is already in the rear-view, and it’s unlikely to shrink.

We don't rely on this continued astronomical growth rate to reach a bullish conclusion. We assume that each factor will slow sharply: token growth decelerates to 24× over 5 years (a number from Goldman Sachs), context discipline/efficiency becomes standard, and various efficiency gains manifest, resulting in forward numbers much more measured than the rear view. Even then, three decelerating curves added together still overrun supply. The last four years don’t need to repeat; they only need to slow gracefully, and the arithmetic still tips into shortage. Set your own assumptions in the calculator.

The mechanics

How this demand turns into memory

AI inference runs on GPUs, and every token a model holds “in context” is bytes that have to sit in fast memory next to the chip, read on every pass. So the three engines largely come down to three things that set the memory bill: how many tasks run at once, how much context each task holds, and how big the model is. Push all three — more agent sessions, longer ones, bigger models — and the tally climbs fast.

An accelerator carries 80 to 192 GB of fast memory next to the chip: an NVIDIA H100 holds 80 GB, an H200 141 GB, a Blackwell B200 180 GB, AMD’s MI300X 192 GB. Weights eat that memory first, and they’re fixed. DeepSeek-R1 is 671 billion parameters; even in its native 8-bit format that’s 671 GB, so the model spans nine H100s before it answers a single request.

Then context piles on top. Agentic models require ever increasing amounts of context for each "turn" to keep track of what they are doing. On Llama-3.1-405B, every token you keep adds about 504 KB to the KV cache — the running memory of the conversation — so a full 128K-token session is roughly 68 GB, and that cache is re-read on every forward pass. Bigger models push on both pools: more layers and heads mean heavier weights and heavier cached tokens. A 70B model caches 320 KB per token; the 405B caches 504 KB.

Generally, the larger the model the more each token of cache needs.

The dials, in plain terms: replicaIndex = how many serving copies the traffic needs · modelScale = frontier model size vs 2026 · weightEff = bytes per parameter after compression · contextBucket = the rolled-up cache pressure per token.

The base case

The base case is a 2.5× shortage, and balance is hard to reach

We look at the HBM that must be installed and serving to run the 2030 workload and compare it to the serving fleet the world’s output can keep in service. A few assumptions stand out as most important. First, cache efficiency: how much paging, quantization, and reuse claw back the context cache by 2030. We assume 4×, which is above history but below theoretical peaks put forth in research papers. Second, the model mix: how much inference runs on large frontier models versus smaller, cheaper ones. Today, frontier-class models account for roughly 70% of inference demand; dialing that up or down moves only the resident-weights slice, so it nudges the total rather than swinging it. Lastly, supply: how much HBM the world will actually be able to make in 2030. Our base case assumes a doubling of annual output, which is based on TrendForce’s analysis. Finally, the fleet: only a share of each year’s output ends up serving inference (~2/3 by 2030; the rest feeds training and other uses), and it serves for about five years before retiring. There are a number of dials here, including projected China supply, which you can play with in the calculator.

You can play with the models in the calculator section, but a few things stand out. Push cache efficiency to 6× — fully solved — and the need only falls to ~22 EB, still a ~2.1× shortage against the fleet. And with 25T-class models, weights are now nearly half the bill, so the model mix matters more than it used to — though even heavy routing to small models only pulls the base to ~2.2×.

The gap also appears to widen every year. Demand compounds about 5.6× by 2030 while output doubles, so each year opens wider than the last:

Weights and cache now split the 2030 bill almost evenly — about 44% each, with scratch taking the rest — since 25T-class models keep weights heavy while usage and state feed the cache. Against a ~10.6 EB serving fleet, 2026’s 1.28× tightness — already enough to sell the market out — widens to 2.5× by 2030. That looks like a structural, widening shortage, and it’s the setup for the rest of the page.

The bear case

What it takes to optimize out of this

Two moves can tip the market into balance: shrink demand, or grow supply faster than the industry says it can. 

The cache efficiency dial (measured vs today) is the major model-efficiency gain, because it directly addresses the biggest contributor to HBM need. 

The HBM annual output dial adjusts how much higher 2030 supply will be than it is today.

The frontier-versus-low-end mix dial sets how much of token demand uses large HBM-resident models (today roughly 70%). Many people mistakenly believe that Chinese models or other open source models are a solution to the memory supply problem, but it appears to be the nature of agentic work, more than the size of the models, that is most material.

It's very difficult for the dials to result in a surplus while maintaining realistic supply assumptions.

The range of outcomes

Six scenarios, and the gap each one leaves

Each rung is a complete, openable scenario — a different read on the two levers that decide it, demand efficiency and the supply ramp. Notice what it takes to clear the shortage: nothing on this ladder does — even the top rung, efficiency solved and output ramping twice as fast as the industry guides, still lands ~1.3× short. Nearly every believable scenario lands at a 2×-to-3× shortage. Click any rung to load its exact dials in the calculator.

There’s no especially comfortable scenario to retreat to. Cache efficiency, the best optimization lever, only pulls the base from 2.5× to about 2.1×; the rest would take a supply ramp far past anyone’s guidance. The whole ladder belongs on the page, not one hero number.

Below is a chart showing how much changing each dial can move the overall situation.

Each bar sweeps one lever across its plausible range; the dark line marks the 2.5× base. Further right = bigger shortage.

Measured against the serving fleet, no single lever closes the gap. The supply ramp gets closest — but output that lands in 2029–30 barely has time to reach the fleet, so even a 6.5× ramp leaves the market ~1.2× short, and balance takes roughly 8×. The demand dials bend the line; none reaches balance alone, and even stacked they only approach it at the aggressive edge. That’s the case in one chart.

The supply side

There are real physical limits to how fast production can scale

Most people admit that demand for AI will explode, but skeptics lean either on efficiency breakthroughs (which our calculator suggests fall short) or massive supply unlocks. Supply will almost certainly continue coming online, but the question is how fast. Industry HBM output runs about 2.8 EB in 2024 and reaches roughly 7.6 EB a year by 2030, around 2.7× over six years and barely a doubling off the model’s 2026 base, decelerating as it goes (Yole Group bit-supply data). That’s the entire planet’s annual production, against demand that wants ~5.6×. Output is unlikely to just double again to catch it, because usable HBM for frontier AI isn’t a raw bit count — it’s a wafer clearing four gates:

TrendForce has HBM wafer input at the top three suppliers climbing from roughly 18% of DRAM wafers in 2025 toward 30% by the end of 2027, with capacity per AI chip rising from 96/192 GB to 216/288 GB and Rubin Ultra expected at 384 GB. That’s a capacity reallocation, not restocking, and reallocation is sticky in both directions.

Micron’s fiscal Q3 2026 recent earnings report called this into focus as well: They've signed 16 strategic customer (long term) agreements spanning 2026–2030, over $100 billion of revenue under minimum-pricing terms, about $22 billion of customer deposits, an HBM4 ramp running ahead of HBM3E, and management still guiding tightness past calendar 2027.The willingness of the hyperscalers to commit to long term memory contracts suggests they are seeing the same thing.

While DRAM is largely a commodity, HBM is much more difficult to manufacture. The clearest evidence is that even incumbents stumble: Samsung, one of the three big DRAM makers, spent roughly 18 months failing and re-submitting its 12-layer HBM3E for NVIDIA qualification before finally clearing it in late 2025 (TrendForce), and NVIDIA is already pushing HBM4 specs higher still (Tom’s Hardware). If a top-three incumbent needs eighteen months to qualify a part, a brand-new entrant — in China or anywhere else — is unlikely to relieve a 2030 shortage on schedule.

Our calculator treats China as a separate pool: you set the year its fabs reach volume and the share of global HBM bits it reaches by 2030, and it's very hard to see it relieving the world's shortage.

The memory makers

A shortage looks close to baked in. What does it do to a P&L?

The model is designed to predict one number: how many exabytes a year short the world runs in 2030. But it's not necessarily immediately clear how that number flows through to the memory maker stocks.

A 2.5x supply/demand imbalance would plausibly flow through to all four of these — the shortage doesn’t stop at the sold-out book; it tends to work its way into pricing, margins, and, eventually, the multiple.

Step 1 is already contracted and public; Micron’s deposits and minimum-price agreements are on the books today. Step 2 tends to follow from a sustained deficit, and we are seeing DRAM prices creep ever higher with little sign of slowing. Step 3 tends to fall out of Step 2, and Step 4 is where a prolonged supply/demand imbalance has historically pointed.

The conclusion

A sold-out market rarely crashes. It reprices.

This massive demand spike, coupled with the difficulty of qualifying new HBM supply across just three suppliers, is the kind of setup markets have historically been slow to price in.

Micron’s recent strength is likely the market beginning to price in these fundamentals: record quarter, $100B+ in minimum-price agreements, tightness guided past 2027. It reads like the brutal down-cycle, run in reverse.

The chain is short. The gap looks structural.

The living monitor

A thesis should be scored, not defended

If the base case is wrong, it won’t show up as “memory was cyclical after all.” It’ll show up as one of these dials crossing one of these triggers — which is what makes this a thesis you can be wrong about rather than a slogan.

Sources

Where the numbers come from

Each source is used only for what it actually proves, and primary releases were checked back to the original.

• PrimaryGoldman Sachs Research — the 24× token frame to ~120 quadrillion tokens/month by 2030. The traffic curve only; a single-analyst forecast, attributed as such.
• PrimaryNVIDIA Rubin & H100 specs — 80 GB HBM3 up to 288 GB HBM4. The per-accelerator HBM step-up behind the track record and the supply ramp.
• PrimaryTrendForce — wafer-input 18%→30% and Rubin Ultra 384 GB, and Samsung’s 18-month HBM3E qualification; the ~2.8→7.6 EB annual-output path comes from Yole Group bit-supply data. The supply side.
• PrimaryMicron FQ3 2026 — $41.5B revenue, 16 SCAs, $100B+ minimum-price, $22B deposits, HBM4 ahead, tightness beyond 2027. The contracted, sold-out book.
• ModeledDynamo & vLLM PagedAttention — why context cache is real serving state, and why it also optimizes.